The present invention relates to a semiconductor design technology, and more particularly to a semiconductor memory device to input and output data and an external signal.
Generally, synchronous semiconductor memory devices perform a signal process operation such that data are stored in memory cells and read out from the cells according to the defined regulation using clock, address, command and data inputted from an external circuit.
In order to use the clock, address, command and data which are applied to the synchronous semiconductor memory devices, it is required to convert the signal characteristics. An input buffer is used for the conversion of the signal characteristics. A semiconductor memory device, which includes the input buffer for the signal characteristics, will be described below.
FIG. 1 illustrates a block diagram of a conventional semiconductor memory device including an I/O unit. Particularly, in FIG. 1, a path between a DQ pad and a data line is depicted at the time of read and write.
The I/O unit of the conventional semiconductor memory device includes a DM pad 10 for receiving a data mask signal DM; a mask input unit 20 for converting output signals of the DM pad 10 into internal voltage signals and aligning them to output alignment mask signals ALGN_DM<0:3>; a DM sense amplifier 25 for sensing and amplifying the alignment mask signals ALGN_DM<0:3> to output mask control signals DM_CTRL<0:3>; a DQ pad 30 for inputting and outputting data DQ; a data input unit 40 for converting output signals of the DQ pad 30 into internal voltage signals and aligning them in order to output alignment data ALGN_DQ<0:3>; a DIN select unit 50 for selecting one from the plurality of the alignment data ALGN_DQ<0:3> in response to write address information signals ADD_WT<13> and ADD_WT<11>; a DIN sense amplifier 55 for sensing and amplifying the selected data from the DIN select unit 50 and applying the amplified signal to global lines GIO_L0<0:3>; a plurality of write driving units 82 for selectively applying data, which are loaded on the corresponding global line GIO_L0<0:3>, to the corresponding data lines LIO in response to the mask control signals DM_CTRL<0:3>; a plurality of read driving units 84 for sensing and amplifying data loaded on the corresponding data lines LIO and applying the amplified data to the corresponding global lines GIO_L0<0:3>; a DOUT select unit 60 for selectively receiving the data loaded on the plurality of the global lines GIO_L0<0:3>, GIO_U0<0:3>, GIO_L7<0:3> and GIO_U7<0:3> in response to bandwidth signals (X16 and X4), a write/read signal WTRDB, an output enable signal PINMUXB and a read address information signals GAX13 and GAY11; and the data output unit 70 for aligning output signals RD_DQ<0:3> of the DOUT select unit 60 and outputting them to the DQ pad 30.
The mask input unit 20 includes a DM buffer unit 22 for converting output signals of the DM pad 10 into internal voltage signals in order to produce internal mask signals INT_DM and a DM alignment unit 24 for aligning the internal mask signals INT_DM in order to output them as the alignment mask signals ALGN_DM<0:3>.
The data input unit 40 includes a DQ buffer unit 42 for converting the output signals of the DQ pad 30 into the internal voltage signals in order to produce internal data signals INT_DQL0 and a DQ alignment unit 44 for aligning output signal of the DQ buffer unit 42 in order to output them as the alignment data ALGN_DQ<0:3>. The data output unit 70 includes a pipe latch unit 74 for aligning the output signals RD_DQ<0:3> of the DOUT select unit 60 to a serial data SR_DQ and a driving unit 72 for driving the serial data SR_DQ to the DQ pad 30.
At a write operation, the DQ pad 30, the data input unit 40, the DIN select unit 50, the plurality of write driving units 82 and the DIN sense amplifier 55 are involved in a data input path and the DM pad 10, the mask input unit 20 and the DM sense amplifier 25 are involved in a mask control signal input path. Moreover, at a read operation, the reading driving unit 84, the DOUT select unit 60 and the data output unit 70 are involved in a data output path.
Meanwhile, in the above-mentioned semiconductor memory device, the data inputted into the DQ pad 30 are respectively applied to the corresponding global lines GIO_L0<0:3>. At this time, the data applied to the global lines GIO_L0<0:3> are changed according to data widths such as 4-bit X4, 8-bit X8 and 16-bit X16. Therefore, the relationship between the DQ pad LDQ0 to LDQ7 and UDQ0 to UDQ7 and the global lines GIO_L0 to GIO_L7 and GIO_U0 to GIO_U7 will be illustrated below based on the data widths X4, X8 and X16 and the operation of the conventional semiconductor memory device will be illustrated.
FIG. 2A illustrates a schematic circuit diagram of an interconnection between the data pads and the global lines in the case of the 16-bit (X16) data width. The DQ pads are coupled to the global lines, respectively. For example, the global line GIO_U0 is coupled to the DQ pad UDQ0 and the global line GIO_L0 is coupled to the DQ pad LDQ0.
Moreover, FIG. 2B illustrates a schematic circuit diagram of an interconnection between the data pads and the global lines in the case of the X8 data width. As shown in FIG. 2B, the global lines GIO_L0 to GIO_L7 and GIO_U0 to GIO_U7 are coupled to only 8 lower pads LDQ0 to LDQ7 of the 16 DQ pads. At this time, upper and lower global lines GIO_L and GIO_U are coupled to one DQ pad LDQ. For example, the DQ pad LDQ0 is coupled to both the upper global line GIO_U0 and the lower global line GIO_L0 and the DQ pad LDQ7 is coupled to the upper global line GIO_U7 and the lower global line GIO_L7. The selection of the global lines commonly coupled to the DQ pads is achieved by the address signals.
Moreover, FIG. 2C illustrates a schematic circuit diagram of an interconnection between the data pads and the global lines in the case of the X4 data width. As shown in FIG. 2C, the global lines GIO_L0 to GIO_L7 and GIO_U0 to GIO_U7 are coupled to only 4 lower pads LDQ0, LDQ1, LDQ2 and LDQ3 of the 16 DQ pads. At this time, two pairs of global lines (two lower global lines and two upper global lines) are coupled to one DQ pad LDQ. For example, the DQ pad LDQ0 is coupled to a pair of the upper and lower global lines GIO_U0 and GIO_L0 and another pair of the upper and lower global lines GIO_U7 and GIO_L7.
As described above, according to the selection of a user, the connection of the DQ pads and the global lines is controlled so that the semiconductor memory device operates in the X16, X8 or X4 data width. In this way, in order to control the interconnection of the global lines, the DQ pads driven in the X16 data width are respectively coupled to the corresponding global lines and the DQ pads driven in the X16 and X8 data widths are coupled to the upper and lower global lines. Finally, the DQ pads which are driven in the X16, X8 and X4 data widths are coupled to the four global lines. For example, in case of the DQ pad UDQ7 driven only in the x16 data width, the DQ pad UDQ7 is coupled to the global line GIO_U7 and the DQ pad LDQ7 driven only in X16 and X8 data widths is coupled to both the upper global line GIO_U7 and the lower global line GIO_L7. Moreover, the DQ pad LDQ0 driven in the X16, X8 and X4 data widths is coupled to the global lines GIO_U7, GIO_L7, GIO_U0 and GIO_L0.
As mentioned above, in case that a plurality of global lines are coupled to one DQ pad, the DIN select unit 50 and the DOUT select unit 60 contribute to the control of the selective interconnection in order to make only one global line coupled to the DQ pad. Therefore, the internal circuit of the DOUT select unit, which makes one of the plurality of global lines coupled to the DQ pad at the read operation, will be described.
FIG. 3 illustrates a schematic circuit diagram of the DOUT select unit 60 described in FIG. 1. Particularly, the DOUT select unit will be illustrated based on one-bit data of the plurality of multiple-bit data.
The DOUT select unit 60 includes a first data select unit 62 for outputting the data loaded on the global line GIO_U0<0> in response to the read address information signals GAX13 and GAY11 in case that the bandwidths are X8 and X4; a second data select unit 64 for outputting the data loaded on the global line GIO_L0<0> in response to the read address information signals GAX13 and GAY11 in case that the bandwidths are X16, X8 and X4; a third data select unit 66 for outputting the data loaded on the global line GIO_U7<0> in response to the read address information signals GAX13 and GAY11 in case the bandwidth is X4; a fourth data select unit 68 for outputting the data loaded on the global line GIO_L7<0> in response to the read address information signals GAX13 and GAY11 in case that the bandwidth is X4; and a latch 69 for inverting and latching a common node output of the first to fourth select units 62, 64, 66 and 68 and for outputting it as a read data RD_DQ<0>.
The first data select unit 62 includes a first NOR gate NR1 for receiving a 16-bit bandwidth signal X16 and the read address information signal GAX13; a first inverter I1 for inverting the read address information signal GAY11, a second inverter I2 for inverting the 16-bit bandwidth signal X16; a second NOR gate NR2 for receiving the write/read signal WTRDB and the output enable signal PINMUXB; a first NAND gate ND1 for receiving output signals of the second NOR gate NR2 and the second inverter I2; a third inverter I3 for inverting an output signal of the first NAND gate ND1; a second NAND gate ND2 for receiving output signals of the first and second inverters I1 and I3 and the first NOR gate NR1, a fourth inverter I4 for outputting a first control signal by inverting an output signal of the second NAND gate ND2; and a first transfer gate TG1 for transferring the data loaded on the global line GIO_U0<0> when the first control signal is activated.
The second data select unit 62 includes the first NOR gate NR1 commonly included in the first data select unit 62 for receiving the 16-bit bandwidth signal X16 and the read address information signal GAX13; a fifth inverter I5 for inverting the output signal of the first NOR gate NR1; the first inverter I1 commonly included in the first data select unit 62 for inverting the read address information signal GAY11; the second NOR gate NR2 commonly included in the first data select unit 62 for receiving the write/read signal WTRDB and the output enable signal PINMUXB; a third NAND gate ND3 for receiving output signals of the first and fifth inverters I1 and I5 and the second NOR gate NR2; a sixth inverter I6 for outputting a second control signal by inverting an output signal of the third NAND gate ND3; and a second transfer gate TG2 for transferring the data loaded on the global line GIO_L0<0> when the second control signal is activated.
The third data select unit 66 includes the first NOR gate NR1 commonly included in the first data select unit 62 for receiving the 16-bit bandwidth signal X16 and the read address information signal GAX13; the first inverter I1 commonly included in the first data select unit 62 for inverting the read address information signal GAY11, an eighth inverter I8 for inverting the output signal of the first inverter I1; the second NOR gate NR2 commonly included in the first data select unit 62 for receiving the write/read signal WTRDB and the output enable signal PINMUXB; a fourth NAND gate ND4 for receiving a 4-bit bandwidth signal X4 and the output of the second NOR gate NR2, an seventh inverter I7 for inverting an output signal of the fourth NAND gate ND4; a fifth NAND gate ND5 for receiving output signals of the seventh and eighth inverters I7 and I8 and the first NOR gate NR1; a ninth inverter I9 for outputting a third control signal by inverting an output signal of the fifth NAND gate ND5; and a third transfer gate TG3 for transferring the data loaded on the global line GIO_U7<0> when the third control signal is activated.
The fourth data select unit 68 includes the first NOR gate NR1 commonly included in the first data select unit 62 for receiving the 16-bit bandwidth signal X16 and the read address information signal GAX13; the fifth inverter I5 commonly included in the second data select unit 64 for inverting the output signal of the first NOR gate NR1; the first inverter I1 commonly included in the first data select unit 62 for inverting the read address information signal GAY11; the eighth inverter I8 commonly included in the third data select unit 66 for inverting the output signal of the first inverter I1; the second NOR gate NR2 commonly included in the first data select unit 62 for receiving the write/read signal WTRDB and the output enable signal PINMUXB; the fourth NAND gate ND4 commonly included in the third data select unit 66 for receiving the 4-bit bandwidth signal X4 and the output of the second NOR gate NR2; the seventh inverter I7 commonly included in the third data select unit 66 for inverting the output signal of the fourth NAND gate ND4; a sixth NAND gate ND6 for receiving the output signals of the fifth, seventh and eighth inverters I5, I7 and I8; a tenth inverter I10 for outputting a fourth control signal by inverting an output signal of the sixth NAND gate ND6; and a fourth transfer gate TG4 for transferring the data loaded on the global line GIO_L7<0> when the fourth control signal is activated.
Next, the operation of the DOUT select unit 60 will be described according to the X16, X8 and X4 data widths.
First, the data select unit is activated when the output enable signal PINMUXB and write/read signal WTRDB have a logic low level, in each case. Under the above circumstance, the 16-bit bandwidth signal X16 becomes a logic high level in the X16 data width. Accordingly, the second data select unit 64 is activated in the X16 data width when the read address information signals GAX13 and GAY11 have a logic low level. That is, the second control signal is activated to a logic high level and the second transfer gate TG2 outputs the data loaded on the global line GIO_L0<0> in response to the activation of the second control signal.
Since the first, third and fourth data select units 62, 66 and 68 inactivate the corresponding control signal to a logic low level in response to the bandwidth signals X16 and X4 and the read address information signal GAY11, the first, third and fourth transfer gates TG1, TG3 and TG4 are not activated. Therefore, the data loaded on the global line GIO_L0<0> are outputted as the read data RD_DQ<0> by the second data select unit 64 at the read operation with the X16 data width.
Moreover, in the X8 data width, the 16-bit bandwidth signal X16 becomes a logic low level the same as the 4-bit bandwidth signal X4. On these conditions, the first data select unit 62 is activated when the read address information signals GAX13 and GAY11 have a logic low level. That is, the first control signal is activated to a logic high level and the first transfer gate TG1 outputs the data loaded on the global line GIO_U0<0> in response to the activation of the first control signal.
However, the second data select unit 64 is activated when the read address information signals GAX13 and GAY11 have logic high and low levels, respectively. That is, the second transfer gate TG2 outputs the data loaded on the global line GIO_L0<0> in response to the activation of the second control signal.
Since the third and fourth data select units 66 and 68 inactivate the corresponding control signal to a logic low level in response to the bandwidth signals X16 and X4 and the read address information signal GAY11, the third and fourth transfer gates TG3 and TG4 are not activated. Therefore, at the read operation with the X8 data width, the first and second data select units 62 and 64 output the data loaded on the global line GIO_U0<0> or GIO_L0<0> as the read data RD_DQ<0> in response to the logic level of the read address information signal GAX13.
Further, in the data width of X4, the first to fourth data select units 62, 64, 66 and 68 activate the first to fourth control signals to a logic high level in response to the logic levels of the read address information signals GAX13 and GAY11. Subsequently, the first to fourth transfer gates TG1, TG2, TG3 and TG4 select one of the data which are loaded on the global lines GIO_U0<0>, GIO_L0<0>, GIO_U7<0> and GIO_L7<0> in response to the activation of the corresponding control signal and outputs the selected data as the read data RD_DQ<0>.
TABLE 1X16 data widthX8 data widthX4 data width(X16 = H,(X16 = L,(X16 = L,ModeX4 = L)X4 = L)X4 = H)Transfer gate TG1InactivationGAX13 = LGAX13 = LGAY11 = LGAY11 = LTransfer gate TG2GAX13 = LGAX13 = HGAX13 = HGAY11 = LGAY11 = LGAY11 = LTransfer gate TG3InactivationInactivationGAX13 = LGAY11 = HTransfer gate TG4InactivationInactivationGAX13 = HGAY11 = L
Therefore, as shown in Table <1>, the DOUT select unit 60 according to the conventional semiconductor memory device makes only the global line GIO_L0<0> coupled to the DQ pad LDQ0 in the X16 data width. In case of the X8 data width, one of the data loaded on the global lines GIO_L0<0> and GIO_U0<0> is selected in response to read address information signal GAX13. In case of the data width of X4, one of the data loaded on the global lines GIO_L0<0>, GIO_U0<0>, GIO_L7<0> and GIO_U7<0> is selected in response to read address information signals GAX13 and GAY11.
Meanwhile, the operation of the conventional semiconductor memory device as shown in FIGS. 1 to 3 will be described below.
First, the write operation at which the data mask signal DM and the data DQ are inputted from an external circuit will be described.
The DM pad 10 receives the data mask signal DM. The DM buffer unit 22 converts the output signals of the DM pad 10 to the internal voltage level and outputs the converted signals as the internal mask signals INT_DM. The DM alignment unit 24 outputs the alignment mask signals ALGN_DM<0:3> by aligning the internal mask signals INT_DM. Next, the DM sense amplifier 25 senses and amplifies the alignment mask signals ALGN_DM<0:3> to outputs them as the mask control signals DM_CTRL<0:3>.
Moreover, the data DQ are applied to the DQ pad 30 from the external circuit. The DQ buffer unit 42 converts the output signals of the DQ pad 30 into the internal voltage level and then outputs the converted signals as the internal data INT_DQL0. The DQ alignment unit 44 outputs the alignment data ALGN_DQ<0:3> by aligning output signals of the DQ buffer unit 42. The DIN select unit 50 selectively outputs the plurality of the alignment data ALGN_DQL0<0:3>, ALGN_DQU0<0:3>, ALGN_DQL7<0:3> and ALGN_DQU7<0:3> by decoding the write address information signals ADD_WT<13> and ADD_WT<11>.
The DIN sense amplifier 55 senses and amplifies the output data of the DIN select unit 50 and then applies the amplified data to the corresponding global lines GIO_L0<0:3>. The write driving units 82 selectively apply the data loaded on the corresponding global lines GIO_L0<0:3> to the data lines LIO in response to the mask control signals DM_CTRL<0:3>. For example, the write driving units 82 do not transfer the data on the global lines GIO_L0<0:3> to the corresponding data lines LIO when the corresponding mask control signals DM_CTRL<0:3> are activated, but transfer the data to the corresponding data line LIO when the corresponding mask control signals DM_CTRL<0:3> are inactivated. That is, the mask control signal DM controls the driving of the write driving units 82 along the same route that the data takes at the write operation. However, since the mask control signal DM is not applied at the read operation, the practical operation does not exist.
On the other hand, the read operation, at which the data are outputted via the DQ pad in response to the corresponding read command, will be described below.
The read driving units 84 sense and amplify the data loaded on the corresponding data lines LIO and then outputs the amplified data to the global lines GIO_L0<0:3>. The DOUT select unit 60 selectively outputs the data loaded on the plurality of the global lines GIO_L0<0:3>, GIO_U0<0:3>, GIO_L7<0:3> and GIO_U7<0:3> in response to the bandwidth signals (X16 and X4), the write/read signal WTRDB and the output enable signal PINMUXB. That is, as shown in FIGS. 2A to 2C, each of the global lines is coupled to the corresponding DQ pad by the DOUT select unit in case of the X16 data width. In case of the X8 data width, two global lines are coupled to the DQ pad and the commonly coupled global lines are selected by the address signal. In case of the X4 data width, four global lines are coupled to the DQ pad and the commonly coupled global lines are also selected by the address signal. The pipe latch unit 74 aligns the plurality of the output signals RD_DQ<0:3> from the DOUT select unit 60 to the serial data SR_DQ and then outputs the aligned data. The driving unit 72 drives the serial data SR_DQ to the DQ pad 30.
In case that the conventional semiconductor memory device is tested by an external test equipment, the number of semiconductor memory devices which can be tested at a time is restricted because the number of pins of the test equipment is restricted. Furthermore, since the initial set-up time to test the semiconductor memory device is longer than the actual test time of the semiconductor memory device, it is necessary to test a large number of the semiconductor memory devices at a time in order to reduce the total test time. For example, it is assumed that two semiconductor memory devices having the X16 data width can be tested by the test equipment which has the restricted number of the pins, the test of four semiconductor memory devices can be carried out at a time in such a manner that the semiconductor memory devices is driven in the X8 data width, in order to reduce the test time by increasing the number of the semiconductor memory devices to be tested at a time. However, even if the number of the semiconductor memory devices which are tested at a time is increased, the reliability of the test is decreased because the test of the semiconductor memory devices is carries out in the X8 data width, but not in the X16 data width of the actual driving condition.